* Delay detection scheme using a 1T delay
* Built-in error correction function using a 2T delay
* Digital PLL clock regeneration
* Block and frame synchr.
Pin No. 3 29 30 31 44 8 9 37 38 39 40 42 Symbol MSK CL CE DI RST TEST1 TEST2 PST PORT0 PORT1 PORT2 S/P 76 kHz MSK signal input CCB serial interface Clock input Data control input Data input Input System reset input pin (negative logic) Test pin 1 (n.
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